One of the stages in the manufacturing process of integrated circuit (IC) devices, such as flash memory, subjects each IC device located on the semiconductor wafer to various electrical tests, known as “wafer sort.” This process evaluates the electronic functionality of each IC device by running analytical electrical tests prior to dicing the wafer and packaging the resulting individual chips. Devices identified as defective are repaired, if possible, while non-repairable devices are sorted out to increase the yield and reduce manufacturing cost. Testing generally involves an external testing apparatus that generates a set of predetermined electrical input signals that are supplied to each IC device to be tested through a multitude of signal probes located on a probe card. The signal probes measure the IC devices' characteristic responses to the input signals, which are then analyzed by the testing apparatus to identify defective IC devices.
With advances in low cost IC production and decreasing physical geometries, the power levels required to operate IC devices is decreasing. For example, stacked dies with small buffers are designed to operate mainly in cross-device communication mode within the same package, requiring very little power. Other devices may be designed without any input/output (IO) functionality. In such designs, the available power might be insufficient to drive electrical signals from the device to be tested through solder bumps or other interconnections to the probe card and/or an external testing apparatus located in the electrical path.
Thus, the inability to communicate with products operating at such low signal strength makes it difficult to test the IC with the current probe card configuration and testing apparatus.